% Start of the revision history table
\addcontentsline{toc}{section}{Revision history}
\begin{versionhistory}
  \vhEntry{4.0}{27-09-2021}{F. P. Schreuder}{Updated documentation with updated Wupper core and register map v2.0}	
  \vhEntry{3.0}{17-05-2019}{F. P. Schreuder}{Updated some descriptions from the FELIX repository}	
  \vhEntry{2.4}{06-11-2017}{R. Blankers}{Added Wishbone bus to the register map}	
  \vhEntry{2.3}{14-04-2015}{F.P. Schreuder}{Updated register map, added description for drivers}	
  \vhEntry{2.1}{14-04-2015}{A.O. Borga}{Uniformed documentatio naming convention (PCIe Engine)}
  \vhEntry{2.0}{21-01-2015}{F.P. Schreuder}{Updated register map}
  \vhEntry{1.9}{09-01-2015}{A.O. Borga}{Reviewed}
  \vhEntry{1.8}{07-01-2015}{F.P. Schreuder}{Modifications for OpenCores}
  \vhEntry{1.7}{29-10-2014}{A.O. Borga}{Major global revision}
  \vhEntry{1.6}{28-10-2014}{A.O. Borga}{Updated PCIe coregen figures, modified appearance of paths throughout the text, fixed typos, updated the simulation and testing sections, added the interrupt handling section, reversed the order of this table}
  \vhEntry{1.5}{23-10-2014}{F.P. Schreuder}{Updated register map, figures and pepo commands, some cosmetic improvements}
  \vhEntry{1.4}{23-09-2014}{J.C. Vermeulen}{Updated figures}
  \vhEntry{1.3}{23-09-2014}{F.P. Schreuder}{Updated pepo commands for memory allocation}
  \vhEntry{1.2}{19-09-2014}{F.P. Schreuder}{Added All pages of Xilinx core wizard}
  \vhEntry{1.1}{19-09-2014}{F.P. Schreuder}{Applied modifications after Andrea's review}  
  \vhEntry{1.0}{16-09-2014}{F.P. Schreuder}{created}  
  \setcounter{table}{0}
\end{versionhistory}
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